This invention relates to methods and apparatus for detecting defects in a semiconductor test structure to thereby predict product yield. More particularly, it relates to voltage contrast techniques for inspecting test structures to predict product yield across multiple product chips having different critical areas.
A voltage contrast inspection of a test structure is accomplished with a scanning electron microscope. The voltage contrast technique operates on the basis that potential differences in the various locations of a sample under examination cause differences in secondary electron emission intensities when the sample is the target of an electron beam. The potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
A secondary electron detector is used to measure the intensity of the secondary electron emission that originates from the path swept by the scanning electron beam. Images may then be generated from these electron emissions. A defective portion can be identified from the potential state or appearance of the portion under inspection. The portion under inspection is typically designed to produce a particular potential and resulting brightness level in an image during the voltage contrast test. Hence, when the scanned portion""s potential and resulting image appearance differs significantly from the expected result, the scanned portion is classified a defect.
One inventive test structure designed by the present assignee is disclosed in co-pending U.S. patent application Ser. No. 09/648,093 by Akella V.S. Satya et al., filed Aug. 25, 2000, which application is incorporated herein in its entirety. This test structure is designed to have alternating high and low potential conductive lines during a voltage contrast inspection. In one inspection application, the low potential lines are at ground potential, while the high potential lines are at a floating potential. However, if a line that is meant to remain floating shorts to an adjacent grounded line, both lines will now produce a low potential during a voltage contrast inspection. If there is an open defect present within a line that is supposedly coupled to ground, this open will cause a portion of the line to be left at a floating potential to thereby produce a high potential during the voltage contrast inspection. Both open and short defects causes two adjacent lines to have a same potential during the voltage inspection.
The results from inspecting a test structure may then be used to predict yield of a product chip that is fabricated with the same process as the test structure. Given a particular defect, yield prediction of a chip (i.e., the probability that the chip will fail) depends on the critical area associated with the particular defect and the probability that the particular defect will fall within the associated critical area. Critical area refers to the total area of the chip as a function of the defect size in which the defect can occur and cause a fault (e.g., a short or open). FIGS. 1A and 1B illustrate the concept of critical area. Each specific configuration of semiconductor circuit, pattern, and test structure has an associated critical area for a given defect size. Additionally, each specific circuit, pattern, and test structure has an associated critical area curve as a function of defect size. FIG. 1A is a diagrammatic top view of a simple test structure 100 having two conductive lines 102a and 102b. The lines 102a and 102b both have a width 104 and a line spacing 106.
FIG. 1B is a graph of critical area as a function of defect size for the test structure 100 of FIG. 1A. A defect 110 that is sized to be less than the line spacing will not cause a fault (e.g., short) in any area of test structure 100. As shown in FIG. 1B, critical area is zero for defects sizes less than width 106. However, a defect 108 having a size (e.g., radius) equal to or greater than the width size 106 will have an associated critical area in which it causes a fault. For example, if the defect 108 is positioned in a narrow area 109 that runs down the centerline between the two lines 102, it will cause a fault by shorting the two lines 102. This narrow area 109 is the critical area for defect 108. The critical area will continue to increase for increasingly sized defects until a critical area plateaus is reached. This plateau is reached at a particular defect size for which the critical area equals the area of the test structure. For this test structure 100, the critical area plateaus at a defect size that is twice the width of the line spacing 106.
Although the yield for a product chip having the same critical area may be predicted based on the test structure, the yield for a product chip having a different critical area than the test structure may not be accurately calculated using the test structure defect data. FIG. 2 shows illustrative plots of critical area for a test structure as a function of defect size, critical area of a particular product chip as a function of defect size, and the number of defects measured for the test structure as a function of defect size.
The defect counts are measured on the test structure, for example, for defect sizes greater than 204. In this example, defects having a size less than 204 are simply not captured because of limitation in the metrology tool. Thus, the defect size distribution (i.e., defect count as a function of defect size) for the test structure may be plotted for defect sizes 204 and higher.
Yield for a particular chip is based on the area under both of its related defect size distribution and critical area curves. Thus, yield for a product chip that has a different critical area than the test structure""s critical area is typically based on the product""s critical area curve (i.e., not the test structure""s critical area curve) and defect size distribution curve. As shown, yield for the product chip is equal to area 206. Although the critical area of the product chip is known, its defect size distribution curve is not known within tolerable certainty. In the illustrated example, defect size distribution has an associated margin of error 208. Unfortunately, this uncertainty is introduced into the yield calculation for the product. As a result, a product yield prediction that is based on a measured defect size distribution curve may be inaccurate and unreliable due to the inaccuracy of the defect size distribution curve.
Accordingly, there is a need for mechanisms for more accurately predicting yield across multiple product chips having different critical areas.
Accordingly, a test chip having a plurality of test structures is provided that is designed so that defect sampling may be customized to obtain different critical areas from the test chip. Each test structure is conceptually divided into a plurality of unit cells (e.g., a pair of grounded and floating conductive lines). The defects of a percentage of unit cells may then be sampled for each test structure to conceptually form a sub test structure that has a different size than the original test structure. The percentage of unit cells that are sampled for each test structure is chosen so as to achieve a specific critical area curve. The defects from each sampled set of unit cells may then combined to determine yield for a product chip having the same specific critical area curve.
These defect sampling techniques are customizable for different product chips having different critical areas to thereby predict product yield for such product chips using the same test chip. In general terms, a first set of unit cells may be sampled from the test structures to predict yield for a product chip having a first critical area, and a second different set of unit cells may be sampled to predict yield for a product chip having a second critical area. Preferably, the granularity of each unit cell is relatively small (e.g., equal to or less than 25 xcexcm) to achieve different critical area curves by combining a different number of unit cells. In one example, the granularity of each cell has a width equal to two line widths (e.g., a floating and grounded line) plus line spacing. Conventional test structures that implement probe pads cannot achieve such small granularity as test structures of the present invention because each probe pad tends to be relatively large (e.g., 100 to 200 xcexcm).
Each unit cell may have different attribute values that affect random yield (herein referred to as xe2x80x9crandomxe2x80x9d attributes). For example, these random attributes may include line spacing and line width. The test structure may also have different values for their random attributes. For example, the test structures may have different combinations of values for line width and spacing.
In one embodiment, the percentages of unit cells that are sampled from the test structures are selected to achieve a specific critical area curve. The sampled defect data is then combined to achieve the specific critical area curve for the sampled test structures. In other words, a critical area curve is formed based on the percentage of unit cells sampled from each different type of test structure. For instance, a first percentage of unit cells are sampled from a first test structure having a first set of line width and spacing values and a second percentage is sampled from a second test structure having a second set of line width and spacing values that differ from the first set. After a particular critical area curve is achieved, random yield for a product chip having the particular critical area may then be predicted from the sampled defect data.
In other specific implementations, one or more test structure also may have one or more attributes that affect systematic yield (herein referred to as xe2x80x9csystematicxe2x80x9d attributes), as compared to the above described random attributes which affect random yield. A test chip may include one or more test structures that include systematic attributes that represent systematic attributes found on various product chips. Defects may then be selectively sampled from one or more test structures that represent a particular product chip. This defect data may be used to predict systematic yield. The predicted systematic yield may then be combined with the predicted random yield to predict total yield for a particular product.
In one embodiment, a method of sampling a test chip having a plurality of test structures is disclosed. In a voltage contrast inspection, defects are sampled from a first set of selected percentage areas of one or more test structures. The sampled defects from the first set of selected percentage areas are combined. The first set of the percentage areas are selected so that the combined sampled defects from the first set of selected percentage areas have an associated first critical area curve.
In a preferred implementation, the first critical area curve substantially matches a first product chip""s critical area curve. In a further embodiment, defects are sampled from a second set of selected percentage areas of one or more test structures. The sampled defects from the second set of selected percentage areas are combined. The second set of the percentage areas are selected so that the combined sampled defects from the second set of selected percentage areas have an associated second critical area curve that differs from the first critical area curve. Preferably, the first critical area curve substantially matches a first product chip""s critical area curve and the second critical area curve substantially matches a second product chip""s critical area curve.
In another aspect, a first yield is predicted based on the sampled defects from the first set of selected percentage areas. The first yield is applicable to any product chip having the same first critical area curve as the sampled defect data from the first set of selected percentage areas. A second yield is predicted based on the sampled defects from the second set of selected percentage areas. The predicted yield is applicable to any product chip having the same first critical area curve as the sampled defect data from the second set of selected percentage areas. In a further implementation, the first and second yields are provided to designers of product chips, and a product chip that has the same characteristics as test structures that were sampled to achieve either the first or second yield, whichever is higher, is designed. In another embodiment, a product chip that excludes the same characteristics as test structures that were sampled to achieve either the first or second yield, whichever is lower, is designed.
In a specific implementation, a first percentage area of a first test structure is sampled for defects and a second percentage area of a second test structure is sampled for defects. The first percentage area differs from the second percentage area. The first test structure has a first set of characteristics that differ from a second set of characteristics of the second test structures. The first and second set of characteristics each include a set of line width and line spacing values.
In yet another embodiment, a first yield is predicted based on the sampled defects from the first set of selected percentage areas. The first yield is applicable to any product chip having the same first critical area curve as the sampled defect data from the first set of selected percentage areas. In a specific aspect, the test structures include random test structures that are designed for accurate prediction of the first yield and systematic test structures that are designed for accurate prediction of a systematic yield for a same type of structure as the systematic test structures. The systematic test structures are selectively sampled for defects so that the systematic yield is predicted for selected types of structures. The first yield is combined with the systematic yield to obtain a total yield. The total yield may be provided to designers of product chips where a product chip is designed based on the provided total yield.
In another aspect, the invention pertains to a computer program product for sampling a test chip having a plurality of test structures using an inspection system. The computer program product includes at least one computer readable medium and computer program instructions stored within the at least one computer readable product configured to cause the inspection system to performed one or more of the above described methods. In another embodiment, the invention pertains to an inspection system for sampling a test chip having a plurality of test structures. The system includes a beam generator for generating an electron beam, a detector for detecting electrons, and a controller arranged to perform one or more of the above described methods.